The present invention relates to circuits with complementary MOS transistors and more particularly to bistable JK flip-flop structures. A typical structure of the type concerned comprises at least three logic gates each of which includes a first group of transistors of a first conduction type and a second group of transistors of a second conduction type, the two groups of transistors being connected in series across the terminals of a voltage supply source and their common connection point forming the output node of the gate. The conduction paths of the said transistors of each group are connected in series and/or in parallel to each other, so that the conduction state of these transistors determines the potential at the output node of the gate, which potential represents the inner variable provided by this gate and may take values substantially equal to those at the two terminals of the voltage supply source, the terminal connected to the first group of transistors being at a potential 1 and that connected to the second group of transistors being at the potential 0. Each transistor is controlled by an inner variable or by an external control variable such as J, K or H, H being a clock signal.
Various structures of bistable JK flip-flops are already known, in particular so-called "master-slave" circuits, circuits using transmission gates and circuits derived from bistable SR flip-flop circuits.
The circuit disclosed in the catalogue of Solid State Scientific Inc., CMOS Integrated Circuits, year 1976, p. 36, circuit SLC 4027A, for example, employs a D flip-flop linked to a combinatorial part. The behaviour of this circuit is insensitive to parasitic effects on the variables J and K and it is free of logical hazards. However, such a structure is quite complex as it includes thirty-six MOS transistors.
Another circuit known as MM 74 C 76 Dual JK flip-flop and appearing in the catalogue of National Semi-Conductor Corporation, year 1973, pages 8-11, is based on the same principle as the previously mentioned circuit and is also insensitive to parasitic noise affecting the variables J and K. However, this circuit requires the presence of the clock variable in the true form (H) and in the inverted form (H), which is a drawback from the point of view of the required surface of the integrated circuit. Moreover, a logical hazard exists due to the delay of H with respect to H, since the variables H and H can momentarily take the same value and short-circuit two nodes having different logic states. It is thus necessary to control the delay of H with respect to H to ensure correct operation. Furthermore, production of these structures in integrated technology has certain drawbacks due to a bad separation of the p- and n-channel transistors of the transmission gates used in this circuit. Finally, the circuit comprises twenty-eight MOS transistors and is thus relatively complicated.
A JK flip-flop structure has also been produced which is derived from a SR flip-flop in which S=JQ and R=KQ. Such a circuit, however, also comprises twenty-eight MOS transistors when it is produced by CMOS technique and it is sensitive to parasitic noise affecting the control variables J and K: The flip-flop should operate only if J=1 and if the edge of the clock signal allows operation. However, a parasitic noise on J could result in an output such that the flip-flop acts in response to the edge of the clock signal even if J is at its level J=0.